Aoximing unveiled its ASMPT advanced packaging solution, directly addressing the pain points of x PO optical interconnection technology in the AI era. News on June 1 (Ace) Optical communications, as the core base of intelligent computing power in the AI era, has entered a new and prosperous industrial development cycle, with x PO technologies such as CPO/NPO/LPO/XPO blooming. In this context, the x PO Empowering AI Data Center Optical Interconnect Forum, jointly organized by China International Optoelectronics Expo and Communication Network, and co-organized by Shenzhen Optics and Optoelectronics Industry Association, Suzhou Optoelectronics Industry Chamber of Commerce, and Suzhou Optoelectronics Communications Association, was grandly held in Shanghai on May 28, 2026. At this forum, Cao Chenyang, the technical market representative of Aoxinming, a sub-brand of ASMPT Group, delivered a keynote speech entitled The Evolution and Industry Outlook of x PO Optical Interconnect Packaging Technology in the Computing Power Era . He not only deeply discussed the memory wall and I/O wall bottlenecks currently faced by AI computing power and the evolution of x PO technology, but also shared the key challenges of packaging technology. Cao Chenyang pointed out that optical interconnect technology has changed from an option to a must-have for AI data centers. x PO technology, represented by CPO (co-packaged optics) and NPO (near-packaged optics), is the core engine that breaks bandwidth limitations and leads the next generation of data center architecture. At the beginning of his speech on the explosion of AI computing power reshaping the semiconductor landscape, Cao Chenyang started from the classic question Can machines think? posed by Turing in 1950, and reviewed the iterative history of AI for more than 70 years, especially the breakthrough progress represented by ChatGPT, DeepSeek and OpenClaw AI agents in recent years. Citing data from the World Semiconductor Trade Statistics (WSTS), he emphasized that global semiconductor sales surged by 26.2% in 2025, reaching US 795.6 billion, and are expected to reach the US 975 billion mark in 2026. AI's strong demand for computing/storage/optical/electricity is the core engine of this round of semiconductor rising cycles, Cao Chenyang said. According to epoch.ai, sales of AI computing power chips have exceeded US 190 billion in 2025. As AI shifts from training to reasoning, the speed and demand for optical modules in AI data centers are rising sharply. He pointed out that traditional data centers and supercomputing centers are evolving into AI data centers, and the optical module speed has jumped from the 100G era to 400G and 800G, and is about to usher in the 1.6T or even 3.2T era. However, AI computing power currently encounters a bottleneck: the growth rate of computing power has exceeded the speed of data transmission. The performance growth of computing chips is 3.2 times every two years, while the growth of memory bandwidth and interconnection bandwidth is only 1.6 times and 1.4 times. The resulting memory wall and IO wall are a core bottleneck restricting the release of AI computing power. And x PO technologies such as NPO and CPO are the key technology trends to break the bottleneck. Cao Chenyang quoted LightCounting data and said that it is expected that 1.6T optical modules will usher in explosive growth this year, and CPO and NPO are expected to begin large-scale deployment in 2028, with a compound annual growth rate of 183% over the five-year period. Technology evolution: from pluggable to deeply integrated In the presentation of the technology roadmap, Cao Chenyang analyzed in detail the technology evolution path from pluggable optical modules (DPO, LPO/LRO, XPO) to integrated optics (NPO, CPO). The first stage of pluggable optics: including DPO, LRO/LPO, and XPO, the optical module is separated from the switch ASIC chip, and the signal is transmitted through the optical cage connector. The second stage of integrated optics: This is the mainstream direction in the future, including NPO - placing the optical engine (OE) on the PCB board and sharing the PCB with the ASIC; and more highly integrated CPO - the optical engine and the ASIC chip share the substrate (Substrate) or even the interposer, which significantly shortens the electrical signal transmission path, reduces power consumption and increases bandwidth. Cao Chenyang mentioned that with the improvement of integration level, packaging technology is moving towards heterogeneous integration. This not only involves the integration of EIC (electronic integrated circuit) and PIC (photonic integrated circuit) inside the light engine, but also involves the system-level integration of the light engine and ASIC/xPU chips. Facing the three core challenges of x PO packaging while looking forward to the technological prospects, Cao Chenyang analyzed the three severe challenges faced by packaging technology of x PO technology on the road to mass production, and introduced in detail the cutting-edge full set of packaging solutions that rely on ASMPT's deep technical heritage and combined with Aoximing's localized service capabilities. One of the key challenges lies in the high-precision heterogeneous integration of EICs and PICs. Due to limitations in the domestic EIC manufacturing process, it is often necessary to use multiple EICs to build a Compound Wafer and bond it with the PIC. This requires extremely high placement accuracy. In response to this, in the advanced packaging equipment matrix of ASMPT and Aoxinming, the NUCLEUS series equipment (with an accuracy of 2 m to 3.5 m) can provide a full range of Fan-out solutions from the wafer level to the board level; for hybrid bonding with higher I/O density, the LITHOBOLT series is a key equipment for the hybrid bonding process, which can achieve alignment accuracy below 100nm The second challenge lies in the warpage and optical port contamination of the wafer-level process. Warpage caused by the mismatch of CTE (coefficient of thermal expansion) of different materials, as well as the contamination of the optical port by flux, are yield killers. In this regard, ASMPT's FIREBIRD series products can effectively control warpage through the TCB (thermal compression bonding) process, with an accuracy of 0.8 m; at the same time, the AOR (active oxide removal) technology can be upgraded to use Fluxless TCB to solve the problem of flux residue from the root cause, achieving clean bonding without flux. The third challenge lies in the maintainability and yield sensitivity of the integration of the optical engine and the ASIC/xPU system. In the CPO architecture, the optical engine and the ASIC/xPU are deeply integrated. Once a single optical engine fails, the entire module will be scrapped. Cao Chenyang took a CPO switch that integrates multiple sets of optical engines as an example. As the number of optical engines increases, the architecture has an obvious yield amplification effect. A decline in the yield of a single device will directly lead to a sharp decline in the yield of the entire machine. In response to this, Cao Chenyang demonstrated the full-process equipment support capabilities of ASMPT and Aoximing, covering everything from wafer dicing, EIC/PIC heterogeneous integration to optical engine and ASIC/xPU system-level assembly, ensuring the ultimate yield through high-precision, high-maturity equipment and processes. These include the widely recognized ASMPT advanced packaging core product portfolio NFL series (NUCLEUS, FIREBIRD, LITHOBOLT), and the ASMPT AMICRA series specially designed for silicon photonics and advanced packaging. In the era of computing power, optical interconnection is the key to breaking through. Opportunities and challenges for 'x' PO packaging technology coexist, Cao Chenyang emphasized in his summary. As a bridge connecting top international technologies and local implementation, Aoximing will rely on ASMPT's leading equipment matrix and continue to join hands with the upstream and downstream industry chains to jointly create an advanced packaging technology ecosystem, accelerate the large-scale commercial implementation of 'x' PO technology, and contribute to the high-quality development of China's semiconductor industry